| 摘要 |
A GOA circuit applied to a liquid crystal display is disclosed, which comprises a plurality of cascaded shift register units, an (N)th level shift register unit is controlled to charge an (N)th level scanning line accordingly. The (N)th level shift register unit includes a pull-up circuit, a pull-down circuit, a pull-down sustain circuit, a pull-up control circuit, a down transfer circuit, and an bootstrap capacitor, and a display device is also disclosed herein. By replacing scanning lines with a constant voltage VDD or two voltages to accomplish the function of down transfer, the loading of scanning lines and the risk which comes with wiring step-by-step are decreased, forward-scanning operation and backward-scanning operation are accomplished accordingly. |
| 主权项 |
1. A GOA (Gate Driver on Array) circuit applied to a liquid crystal display, comprising:
a plurality of cascaded shift register units, an (N)th level shift register unit being controlled to charge an (N)th level scanning line (G(N)) accordingly, the (N)th level shift register unit includes a pull-up circuit (200), a pull-down circuit (400), a pull-down sustain circuit (600), a pull-up control circuit (100), a down transfer circuit (300), and an bootstrap capacitor (Cb); the pull-up circuit (200), the pull-down sustain circuit (600), and the bootstrap capacitor (Cb) being individually connected with a gate signal point Q(N) and the Nth level scanning line (G(N)); the pull-up control circuit (100) and the down transfer circuit (300) being individually connected with the gate signal point Q(N); the pull-down circuit (400) being connected with a start signal (ST(N+1)) of an (N+1)th level shift register; the pull-up control circuit (100 being connected with a start signal (ST(N−1)) of an (N−1)th level shift register; the pull-down sustain circuit (600) comprises:
a first TFT (Thin film transistor) (T32) comprises a gate of the first TFT (T32) being connected with a first circuit point (P(N)), a drain of the first TFT (T32) being connected with the (N)th level scanning line (G(N)), and a source of the first TFT (T32) being connected with a first direct-current voltage (VSS1);a second TFT (T42), a gate of the second TFT (T42) being connected with the first circuit point ((P(N)), a drain of the second TFT (T42) being connected with the gate signal point (Q(N)), and a source of the second TFT (T42) being connected with a second direct-current voltage (VSS2);a third TFT (T52), a gate of the third TFT (T52) being connected with the gate signal point (Q(N)), a drain of the third TFT (T52) being connected with a source signal point (S(N)), and a source of the third TFT (T52) being connected with the first direct-current voltage (VSS1);a fourth TFT (T51), and a source of the fourth TFT (T51) being connected with a source signal point (S(N)), a gate and a drain of the fourth TFT (T51) being connected with a first clock signal (LC1);a fifth TFT (T53), a gate of the fifth TFT (T53) being connected with the source signal point (S(N)), a drain of the fifth TFT (T53) being connected with the first clock signal (LC1), and a source of the fifth TFT (T53) being connected with the first circuit point (P(N));a sixth TFT (T54), a gate of the sixth TFT (T54) being connected with a second clock signal (LC2), a drain of the sixth TFT (T54) being connected with the first clock signal (LC1), and a source of the sixth TFT (T54) being connected with the first circuit point (P(N));a seventh TFT (T72), a gate of the seventh TFT (T72) being connected with the first circuit point (P(N)), a drain of the seventh TFT (T72) being connected with a start signal (ST(N)) of an (N)th level shift register, and a source of the seventh TFT (T72) being connected with the second direct-current voltage (VSS2);an eighth TFT (T33), a gate of the eighth TFT (T33) being connected with a second circuit point (K(N)), a drain of the eighth TFT (T33) being connected with the (N)th level scanning line (G(N)), and a source of the eighth TFT (T33) being connected with the first direct-current voltage (VSS1);a ninth TFT (T43), a gate of the ninth TFT (T43) being connected with the second circuit point (K(N)), a drain of the ninth TFT (T43) being connected with the gate signal point (Q(N)), and a source of the ninth TFT (T43) being connected with the second direct-current voltage (VSS2);a tenth TFT (T62), a gate of the tenth TFT (T62) being connected with the gate signal point (Q(N)), a drain of the tenth TFT (T62) being connected with a drain signal point (T(N)), and a source of the tenth TFT (T62) being connected with the first direct-current voltage (VSS1);an eleventh TFT (T61), and a source of the eleventh TFT (T61) being connected with the drain signal point (T(N)), a gate and a drain of the eleventh TFT (T61) being connected with the second clock signal (LC2);a twelfth TFT (T63), a gate of the twelfth TFT (T63) being connected with the drain signal point (T(N)), a drain of the twelfth TFT (T63) being connected with the second clock signal (LC2), and a source of the twelfth TFT (T63) being connected with the second circuit point (K(N));a thirteenth TFT (T64), a gate of the thirteenth TFT (T64) being connected with the first clock signal (LC1), a drain of the thirteenth TFT (T64) being connected with the second clock signal (LC2), and a source of the thirteenth TFT (T64) being connected with the second circuit point (K(N));a fourteenth TFT (T73), a gate of the fourteenth TFT (T73) being connected with the second circuit point (K(N)), a drain of the fourteenth TFT (T73) being connected with the start signal (ST(N)) of an (N)th level shift register, and a source of the fourteenth TFT (T73) being connected with the second direct-current voltage (VSS2); anda fifteenth TFT (T55), a gate of the fifteenth TFT (T55) being connected with the gate signal point (Q(N)), a drain of the fifteenth TFT (T55) being connected with the first circuit point (P(N)), and a source of the fifteenth TFT (T55) being connected with the second circuit point (K(N)); while in operation, frequencies of the first clock signal (LC1) and the second clock signal (LC2) are lower than that of an (N) level clock signal (CK(N)), a process of charging the first circuit point (P(N)) by the first clock signal (LC1) and a process of charging the second circuit point (K(N)) by the second clock signal (LC2) are performed alternatingly, wherein the pull-up circuit (200) comprises a sixteenth TFT (T21), a gate of the sixteenth TFT (T21) being connected with the gate signal point (Q(N)), a drain of the sixteenth TFT (T21) being connected with the (N) level clock signal (CK(N)), and a source of the sixteenth TFT (T21) being connected with the (N)th level scanning line (G(N)). |
