| 摘要 |
An asymmetric hysteretic controller comprises an analog comparator coupled with a fast slew rate DAC, or a digital comparator coupled with an ADC plus some digital control logic. The comparator, analog or digital, operates as a sequential windowed comparator having high and low limits. The sense parameter is compared to a high or a low limit and when the sense parameter reaches the selected high or low limit, the controlled device is turned off or on, respectively. When the hysteretic controller state comparison reversal occurs: (a) the comparator output may be blanked by the control logic, (b) the comparator polarity may be reversed by the control logic, (c) the control logic may command the other process limit to be selected for comparison with the sense parameter, and (d) then the comparator output may be re-enabled. |
