HIGH PERFORMANCE SHIFTER CIRCUIT

摘要

An improved shifter design for high-speed data processors is described. The shifter may include a first stage, in which the input bits are shifted by increments of N bits where N>1, followed by a second stage, in which all bits are shifted by a residual amount. A pre-shift may be removed from an input to the shifter and replaced by a shift adder at the second stage to further increase the speed of the shifter.

主权项

1. A digital M-bit shifter circuit comprising:
a first stage comprising digital buffers configured to shift the M bits by increments of N, where N>1; and a second stage comprising digital buffers configured to shift the M bits by an amount less than or equal to N.