High utilization multi-partitioned serial memory

摘要

A memory device that includes an input interface that receives instructions and input data on a first plurality of serial links. The instructions and input data are deserialized on the memory device, and are provided to a memory controller. The memory controller initiates accesses to a memory core in response to the received instructions. The memory core includes a plurality of memory partitions, which are accessed in a cyclic and overlapping manner. This allows each memory partition to operate at a slower frequency than the serial links, while properly servicing the received instructions. Accesses to the memory device are performed in a synchronous manner, wherein each access exhibits a known fixed latency.

主权项

1. A memory device comprising:
an input interface that receives instructions on a first plurality of serial links; a memory core comprising a plurality of memory partitions; and a memory controller coupled to receive the instructions from the input interface, and in response, initiate accesses to the memory partitions of the memory core in a cyclic manner, wherein the accesses are performed with a fixed latency from a time the input interface receives the instructions on the first plurality of serial links, wherein each of the accesses to the memory partitions is initiated in the memory partition with a fixed delay from a time the input interface receives the corresponding one of the instructions on the first plurality of serial links.