发明名称 |
GPU based parallel image processing at thin client |
摘要 |
Disclosed herein is a computing device that includes: a processor; a graphic processing unit having N graphic processing cores, N being an integer greater than 1; a random access memory (RAM); a video port; a non-volatile memory, and a display processing unit. The non-volatile memory stores a virtual desktop client (VDC). The VDC can communicate with a first virtual machine (VM) of a hypervisor running on a remote computing device and receive an encoded image frame from the first VM; instruct the plurality of graphic processing cores to decode the encoded image frame in parallel; and generate a decoded image frame of the encoded image frame. The display processing unit can generate display signals representing the decoded image frame and transmit the display signals to the video port. |
申请公布号 |
US9342859(B2) |
申请公布日期 |
2016.05.17 |
申请号 |
US201314060165 |
申请日期 |
2013.10.22 |
申请人 |
AMERICAN MEGATRENDS, INC. |
发明人 |
Ayanam Varadachari Sudan;Christopher Samvinesh;Subramanian Yugender P. |
分类号 |
G06T1/20;G06T1/60;G06F3/14 |
主分类号 |
G06T1/20 |
代理机构 |
Locke Lord LLP |
代理人 |
Locke Lord LLP ;Xia, Esq. Tim Tingkang |
主权项 |
1. A computing device comprising:
a processor; a graphic processing unit having N graphic processing cores, N being an integer greater than 1; a random access memory (RAM), having a general memory area that is utilized by the processor, and a graphic memory area that is utilized by the graphic processing unit; a video port; a non-volatile memory storing a virtual desktop client (VDC) configured to, when executed at the processor,
communicate with a first virtual machine (VM) of a hypervisor running on a remote computing device and receive an encoded image frame from the first VM, wherein the encoded image frame include a plurality of encoded image tiles,store the plurality of encoded image tiles of the encoded image frame to the general memory area,copy a first group of N encoded image tiles of the plurality of encoded image tiles to the graphic memory area,instruct the N graphic processing cores to concurrently decode the first group of encoded image tiles, andgenerate a decoded image frame of the encoded image frame; and a display processing unit, configured to generate display signals representing the decoded image frame and transmit the display signals to the video port. |
地址 |
Norcross GA US |