Temperature compensated PLL calibration

摘要

In some embodiments, provided are AFC circuits and methods for calibrating a second setting of an oscillator while a first setting is controlled by a temperature compensated control.

主权项

1. A chip, comprising:
an oscillator with first and second settings for controlling an output frequency; a temperature compensated circuit to provide the first setting based on a chip temperature during a calibration mode, wherein the temperature compensated circuit includes an on-die temperature sensor, wherein the temperature compensated circuit is to generate a control voltage that causes the second setting to be set so that the first setting is at a maximum Kvco for a temperature that is within a middle 25% portion of an operating temperature range; and calibration logic to adjust the second setting, in a closed loop configuration, until the output frequency is sufficiently close to a target frequency during the calibration mode such that during an operational mode the calibration logic is to set the second setting to select almost the same capacitance code for at least two temperature points, wherein the calibration logic is operable to reduce loop bandwidth and jitter peaking variation associated with a Phase Locked Loop (PLL); and wherein the PLL is locked prior to the temperature compensated circuit and calibration logic are to operate.