Boosted read write word line

摘要

One or more techniques or systems for boosting a read word line (RWL) or a write word line (WWL) of a two port synchronous random access memory (SRAM) bit cell array are provided herein. In some embodiments, a boosted control block is configured to generate a boosted word line signal configured to operate a RWL, a WWL, or a read write word line (RWWL). In some embodiments, the boosted word line signal includes a first stage and a second stage. For example, the first stage is associated with a first stage voltage level at a positive supply voltage (Vdd) voltage level and the second stage is associated with a second stage voltage level above the Vdd voltage level. In this manner, a read or write operation is boosted for an SRAM bit cell, because the second stage boosts a corresponding transistor in the SRAM bit cell, for example.

主权项

1. A boosted control block, comprising:
a delay module coupled to at least one of a boosted read enabled pulse (RENP) line or a boosted write enabled pulse (WENP) line; a first NAND gate comprising a first NAND input, a second NAND input, and a first NAND output, wherein:
the first NAND input is coupled to the delay module; andthe second NAND input is coupled to the at least one of the RENP line or the WENP line; a first inverter comprising a first inverter input and a first inverter output, wherein:
the first inverter input is coupled to the first NAND output, andthe first inverter output is configured to generate a first word line signal at the first inverter output; a second inverter comprising a second inverter input and a second inverter output, wherein the second inverter input is coupled to the first inverter output; a third inverter comprising a third inverter input and a third inverter output, wherein the third inverter input is coupled to the second inverter output; and a coupled capacitor coupled to the third inverter output, wherein the coupled capacitor is configured to generate a second boosted word line signal.