发明名称 Memory macro with a voltage keeper
摘要 A memory macro includes a first data line, a second data line, a first switch and a voltage keeper. The first switch is configured between the first data line and the second data line. The voltage keeper is electrically coupled to the second data line. The voltage keeper is configured to control a voltage level at the second data line in response to the voltage level at the second data line during the first switch electrically couples the second data line to the first data line.
申请公布号 US9343125(B2) 申请公布日期 2016.05.17
申请号 US201514620769 申请日期 2015.02.12
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. 发明人 Tao Derek C.;Wang Bing;Fan Allen;Tang Yukit;Lum Annie-Li-Keow;Hsu Kuoyuan
分类号 G11C7/10;G11C7/12;G11C8/00;G11C7/18;G11C11/419 主分类号 G11C7/10
代理机构 WPAT, P.C., Intellectual Property Attorneys 代理人 WPAT, P.C., Intellectual Property Attorneys ;King Anthony
主权项 1. In a memory macro comprising a memory array, a plurality of first data lines associated with memory cells of the memory array, and a second data line associated with the memory array, a circuit comprising: a first switch configured between a first one of the first data lines and a second data line, wherein the first switch is configured to electrically couple the second data line to the first one of the first data lines when a memory cell associated with the first one of the first data lines is accessed.
地址 Hsinchu TW