发明名称 INSTRUCTION AND LOGIC FOR BOYER-MOORE SEARCH OF TEXT STRINGS
摘要 Instructions and logic provide extended vector suffix comparisons for Boyer-Moore searches. Some embodiments, responsive to an instruction specifying: a pattern source operand and a target source operand, compare each of m data elements of the pattern operand with each data element of the target operand. A first and second equal ordered aggregation operation are performed from the comparisons according to the m data elements of the pattern source operand. A result of the first and second aggregation operations indicating whether or not a possible match exists between the m data elements of the pattern source operand and d data element positions relative to data elements of the target source operand is stored. Ordering of the data elements of the pattern and the target operands may be reversed for the second aggregation operation, and d may be a sum of m−1 and the quantity of target operand elements in some embodiments.
申请公布号 US2016132330(A1) 申请公布日期 2016.05.12
申请号 US201614997417 申请日期 2016.01.15
申请人 Intel Corporation 发明人 Kuo Shih J.
分类号 G06F9/30 主分类号 G06F9/30
代理机构 代理人
主权项 1. A processor comprising: a first register comprising a first plurality of m data fields to store values of m data elements; a decode stage to decode a first instruction specifying: a pattern source operand specifying the first register, and a target source operand; and an execution unit, responsive to the decoded first instruction, to: compare each data element of the pattern source operand with each data element of the target source operand;perform a plurality of equal ordered aggregation operations from the comparisons according to the m data elements of the pattern source operand; andstore a result of the plurality of aggregation operations indicating whether or not a match exists between the m data elements of the pattern source operand with d data element positions relative to data elements of the target source operand.
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