发明名称 DATA PROCESSING DEVICE AND DATA PROCESSING SYSTEM
摘要 A data processing device includes a first power-on reset circuit, a second power-on reset circuit with a higher power consumption and a higher reset voltage accuracy than said first power-on reset circuit, a low voltage detect circuit, a storage unit storing information for determining whether to keep said second power-on reset circuit and said low voltage detect circuit in an active state or an inactive state, a central processing unit initialized in a response to respective outputs of said first and second power-on reset circuits and setting said information in said storage unit, and a power supply node providing a power to the data processing device.
申请公布号 US2016132100(A1) 申请公布日期 2016.05.12
申请号 US201514982954 申请日期 2015.12.29
申请人 Renesas Electronics Corporation 发明人 TAKAHASHI Masaru;ISHIKURA Hiromichi
分类号 G06F1/32;H03K17/22;G06F1/24 主分类号 G06F1/32
代理机构 代理人
主权项 1. A data processing device, comprising: a first power-on reset circuit; a second power-on reset circuit with a higher power consumption and a higher reset voltage accuracy than said first power-on reset circuit; a low voltage detect circuit; a storage unit storing information for determining whether to keep said second power-on reset circuit and said low voltage detect circuit in an active state or an inactive state; a central processing unit initialized in a response to respective outputs of said first and second power-on reset circuits and setting said information in said storage unit; and a power supply node providing a power to the data processing device, wherein said first power-on reset circuit includes an internal node that is charged to have a variable potential as a potential of the power supply node changes, wherein the data processing device is configured to select one of a first operation and a second operation in a standby mode, wherein, in the first operation, said first power-on reset circuit with a lower reset voltage is enabled, while said low voltage detect circuit and said second power-on reset circuit are enabled, and wherein, in the second operation, said first power-on reset circuit with the lower reset voltage is enabled, while said low voltage detect circuit and said second power-on reset circuit are disabled.
地址 Tokyo JP