| 发明名称 | Passivation scheme | ||
| 摘要 | An integrated circuit includes a conductive pad disposed over a substrate. A first passivation layer is disposed over the conductive pad. A second passivation layer is disposed over the first passivation layer. A stress buffer layer is disposed over the second passivation layer. A conductive interconnect layer is over and coupled to the conductive pad and over the stress buffer layer with the conductive interconnect layer adjoining sidewalls of the first passivation layer and the stress buffer layer. | ||
| 申请公布号 | US9337133(B2) | 申请公布日期 | 2016.05.10 |
| 申请号 | US201414276702 | 申请日期 | 2014.05.13 |
| 申请人 | Taiwan Semiconductor Manufacturing Company, Ltd. | 发明人 | Chen Hsien-Wei |
| 分类号 | H01L21/44;H01L23/498;H01L23/532;H01L21/768;H01L21/3105 | 主分类号 | H01L21/44 |
| 代理机构 | Slater & Matsil, L.L.P. | 代理人 | Slater & Matsil, L.L.P. |
| 主权项 | 1. An integrated circuit comprising: a conductive pad disposed over a substrate; a first passivation layer disposed over the conductive pad; a second passivation layer disposed over the first passivation layer; a stress buffer layer disposed over the second passivation layer; and a conductive interconnect layer over and coupled to the conductive pad and over the stress buffer layer, the conductive layer directly contacting sidewalls of the first passivation layer and the stress buffer layer, the stress buffer layer extending along a top surface and a sidewall of the second passivation layer and directly contacting the first passivation layer. | ||
| 地址 | Hsin-Chu TW | ||