Liquid crystal display device and method for driving auxiliary capacitance lines

摘要

Provided is a liquid crystal display device with reduced power consumption employing a CS drive method.;A CS driver (500) consists of a CS shift register (510) and a CS output portion (520). The CS shift register (510) outputs control signals (COUT(1) to COUT(m)) in accordance with a CS clock signal CCK. The CS output portion (520) outputs auxiliary capacitance signals (CSS(1) to CSS(m)) in accordance with the control signals (COUT(1) to COUT(m)), respectively. An idle period (T2) is set following a scanning period (T1). During the idle period (T2), the CS driver (500) is driven in accordance with the CS clock signal (CCK) at an idle-period CS frequency (fcck2). The idle-period CS frequency (fcck2) is lower than a scanning-period CS frequency (fcck1).

主权项

1. A liquid crystal display device comprising:
a display portion including a plurality of video signal lines, a plurality of scanning signal lines crossing the video signal lines, a plurality of pixel forming portions including respective pixel electrodes arranged in a matrix so as to correspond to the video signal lines and the scanning signal lines, a plurality of auxiliary capacitance lines arranged along the scanning signal lines, and auxiliary capacitors formed between the auxiliary capacitance lines and the pixel electrodes corresponding to the scanning signal lines along the auxiliary capacitance lines; a display control circuit for generating clock signals alternating between on- and off-levels cyclically; a scanning signal line driver circuit for driving the scanning signal lines such that a scanning period in which the scanning signal lines are selected sequentially and an idle period in which all of the scanning signal lines are in an unselected state alternate with each other in cycles of a frame period consisting of the scanning period and the idle period; and an auxiliary capacitance line driver circuit formed integrally with the display portion to drive the auxiliary capacitance lines independently of one another in accordance with auxiliary capacitance clock signals included in the clock signals, wherein, the auxiliary capacitance line driver circuit includes a first shift register with a plurality of first bistable circuits cascaded to one another, the first shift register sequentially setting output signals from the first bistable circuits to an on-level in accordance with first shift operation clock signals included in the auxiliary capacitance clock signals, and the first shift operation clock signals have a lower frequency during the idle period than during the scanning period.