Equalization for high speed input/output (I/O) link

摘要

Described are systems and apparatuses to mitigate the timing margin loss caused by inter-symbol interference (ISI) in high speed input/output (I/O) interfaces. Data dependent jitter (DDJ) compensation techniques that may be utilized in the transmission or receiving circuitry of the I/O interface, including capturing bit data values of a data signal prior to an identified data transition, and delaying/advancing the transmission/reception the data signal or a corresponding clock signal based on these bit data values.

主权项

1. An apparatus comprising:
a data receiver to receive a data signal; a clock/strobe receiver to receive a clock/strobe signal; a data signal tap/register to capture, in response to an identified data transition in the data signal, a first and a second bit values of the data signal prior to the identified data transition; a floating data signal tap/register to capture, in response to the identified data transition in the data signal, a combination of bit values prior to the first and second bit values, wherein the first and second bit values include two bits of the data signal immediately prior to the identified data transition; and an equalization circuit to delay reception of at least one of the data signal or the clock/strobe signal at a time of the data transition based, at least in part, on the first and second bit values and the identified data transition.