Phase change memory coding

摘要

An integrated circuit phase change memory can be pre-coded by inducing a first resistance state in some cells and the memory, and a second resistance state and some other cells in the memory to represent a data set. The integrated circuit phase change memory is mounted on a substrate after coding the data set. After mounting the integrated circuit phase change memory, the data set is read by sensing the first and second resistance states, and changing cells in the first resistance state to a third resistance state and changing cells in the second resistance state to a fourth resistance state. The first and second resistance states maintain a sensing margin after solder bonding or other thermal cycling process. The third and fourth resistance states are characterized by the ability to cause a transition using higher speed and lower power, suitable for a mission function of a circuit.

主权项

1. An integrated circuit, comprising:
an array of phase change memory cells; sensing circuits coupled to the array, the sensing circuits having a first mode and a second mode, the first mode sensing data values in the array in response to first and second resistance states, and the second mode sensing data values in the array in response to third and fourth resistance states, wherein the first and second resistance states represent a first and second data values respectively, and the third and fourth resistance states represent the first and second data values respectively; and control circuits and biasing circuits coupled to the array arranged to execute transition processes to read a data set with the sensing circuits in the first mode by sensing the first and second resistance states, and to change cells in the first resistance state to the third resistance state and to change cells in the second resistance state to the fourth resistance state so that the data set is readable with the sensing circuits in the second mode, to execute write processes to write data in the array by inducing the third and fourth resistance states in addressed cells, and to execute read processes to read data in the array with the sensing circuits in the second mode by sensing the third and fourth resistance states, wherein the control circuits and biasing circuits are arranged to induce the first resistance state by applying a current pulse having a first magnitude and first duration, and to induce the second resistance state by applying a current pulse having a second magnitude and a second duration, and wherein the first duration is greater than the second duration, and wherein the first and second magnitudes are less than a magnitude applied to induce an amorphous phase in an active region in a cell in the array, and the first magnitude is greater than the second magnitude.