Removing deterministic phase errors from fractional-N PLLs

摘要

Methods and devices for phase adjustment include a phase detector that is configured to compare a reference clock and a feedback clock and to generate two output signals. A difference in time between pulse widths of the two output signals corresponds to a phase difference between the reference clock and the feedback clock. A programmable delay line is configured to delay an earlier output signal in accordance with a predicted deterministic phase error. An oscillator is configured to generate a feedback signal in accordance with the delayed output signal. A divider is configured to divide a frequency of the oscillator output by an integer N. The integer N is varied to achieve an average fractional divide ratio and the predicted deterministic phase error is based on the average divide ratio and an instantaneous divide ratio.

主权项

1. A phase-locked loop, comprising:
a phase detector, configured to generate two output signals, wherein a difference in time between pulse widths of the two output signals corresponds to a phase difference between a reference clock and a feedback clock; a programmable delay line, configured to delay an earlier output signal in accordance with a predicted deterministic phase error; an oscillator configured to generate a feedback signal in accordance with the delayed output signal; and a divider configured to divide a frequency of the oscillator output by an integer N, wherein the integer N is varied to achieve an average fractional divide ratio.