Bidirectional shift register and image display device using the same

摘要

A bidirectional shift register capable of performing a stable shift operation in both directions and an image display device using the same are provided. In forward shift operation, when reference point N1 is at H level, (n+4)-th unit register circuit as a rear stage of the bidirectional shift register outputs pulse G(n+4) in synchronization with clock pulse V (n+4) inputted to (n+4)-th unit register circuit. A backward direction trigger signal VSTB is generated not only at the time of start of backward shift, but also, for example, in period (time t4 to t5) of one-phase clock immediately after G(n+4) is outputted in vertical blanking interval of the forward shift. The backward direction trigger signal VSTB is inputted to gate of a transistor provided to set reference point N1 of (n+4)-th unit register circuit to H level at the time of start of the backward shift.

主权项

1. A bidirectional shift register comprising:
a shift register part that includes N (N is an integer of 6 or more) cascade-connected unit register circuits and outputs an output pulse G(k) of a k-th unit register circuit (k for all integers of 1≦k≦N) in a shift sequence of one of a forward direction and a backward direction; a clock signal generation part that supplies M-phase (M is an integer of 3 or more) clock pulses to the respective unit register circuits of the shift register part sequentially in the forward direction at a time of a forward shift operation of the shift register part or sequentially in the backward direction at a time of a backward shift operation; and a trigger signal generation part that generates a forward direction trigger signal which is a pulse which rises to High level at a time of start of the forward shift and in a vertical blanking interval of the backward shift, and generates a backward direction trigger signal which is a pulse which rises to High level at a time of start of the backward shift and in a vertical blanking interval of the forward shift, wherein the k-th unit register circuit includes a forward direction set terminal, a backward direction set terminal, a forward direction reset terminal, a backward direction reset terminal, a set circuit to set a potential at a reference point to a first potential when a set signal is inputted to one of the set terminals, a reset circuit, being separated from the set circuit to set the potential at the reference point to a second potential when a reset signal is inputted to one of the reset terminals, and an output circuit to output the output pulse G(k) in synchronization with the inputted clock pulse in a state where the reference point is at the first potential, when αf is an integer of one or more, αb is an integer of one or more, βf is an integer of two or more, and βb is an integer of two or more, and αf<βbN−βf are dummy register circuits, in a first case that k>αf for the forward shift operation, in the set circuit of the k-th unit register circuit, an output pulse G(k−αf) (k>αf) is inputted as the set signal to the forward direction set terminal, in a second case that k≦αf for the forward shift operation, in the set circuit of the k-th unit register circuit, the forward direction trigger signal is inputted as the set signal to the forward direction set terminal, in a third case that k≦N−αb for the backward shift operation, in the set circuit of the k-th unit register circuit, an output pulse G(k+αb) is inputted as the set signal to the backward direction set terminal, in a fourth case that k>N-ab for the backward shift operation, in the set circuit of the k-th unit register circuit, the backward direction trigger signal is inputted as the set signal to the backward direction set terminal, in a fifth case that k≦N−βf for the forward shift operation, in the reset circuit of the k-th unit register circuit, an output pulse G(k+βf) is inputted as the reset signal to the forward direction reset terminal, in a sixth case that k>N−βf for the forward shift operation, in the reset circuit of the k-th unit register circuit, the forward direction trigger signal is inputted as the reset signal to the forward direction reset terminal, and in the set circuit of the k-th unit register circuit, the backward direction trigger signal is inputted to the backward direction set terminal after the output circuit of the k-th unit register circuit output the output pulse G(k), in a seventh case that k>βb for the backward shift operation, in the reset circuit of the k-th unit register circuit, an output pulse G(k−βb) is inputted as the reset signal to the backward direction reset terminal, and in an eighth case that k≦βb for the backward shift operation, in the reset circuit of the k-th unit register circuit, the backward direction trigger signal is inputted as the reset signal to the backward direction reset terminal, and in the set circuit of the k-th unit register circuit, the forward direction trigger signal is inputted to the forward direction set terminal after the output circuit of the k-th unit register circuit output the output pulse G(k).