| 摘要 |
Method of automatic synthesis of circuits comprising the generation of a network of regular processes reading or writing data in channels, according to which a single producer process is authorized to write in a channel and a single consumer process is authorized to read in a channel; and a synchronization unit associated with said channel authorizes or disables the implementation of a new iteration of said producer process, respectively consumer process, as a function of a comparison of a position of execution determined as a function of the value of a new iteration collected from the producer process, respectively consumer process, and of a position of execution determined as a function of a last iteration value collected from the consumer process, respectively producer process. |
