发明名称 Power Semiconductor Module Having a Direct Copper Bonded Substrate and an Integrated Passive Component, and an Integrated Power Module
摘要 A power semiconductor module includes a direct copper bonded (DCB) substrate having a ceramic substrate, a first copper metallization bonded to a first main surface of the ceramic substrate and a second copper metallization bonded to a second main surface of the ceramic substrate opposite the first main surface. The power semiconductor module further includes a power semiconductor die attached the first copper metallization, a passive component attached the first copper metallization, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component. An integrated power module and a method of manufacturing the integrated power module are also provided.
申请公布号 US2016126192(A1) 申请公布日期 2016.05.05
申请号 US201414529371 申请日期 2014.10.31
申请人 Infineon Technologies AG 发明人 Hohlfeld Olaf;Hoegerl Juergen;Beer Gottfried;Hoier Magdalena;Meyer-Berg Georg
分类号 H01L23/538;H01L21/48;H01L21/56 主分类号 H01L23/538
代理机构 代理人
主权项 1. An integrated power module, comprising: a power semiconductor module, comprising: a first power semiconductor die attached to a metallized side of an insulating substrate;a first isolation layer encapsulating the first power semiconductor die; anda first structured metallization layer on the first isolation layer and electrically connected to the first power semiconductor die by at least a first plurality of electrically conductive vias that extend through the first isolation layer; a second isolation layer on the power semiconductor module; a second plurality of electrically conductive vias extending through the second isolation layer to the first structured metallization layer; and a first logic or passive semiconductor die encapsulated in the second isolation layer or in an isolation layer above the second isolation layer, the first logic or passive semiconductor die being electrically connected to the first power semiconductor die by at least the first structured metallization layer and the first plurality of electrically conductive vias, or to another semiconductor die disposed within the integrated power module.
地址 Neubiberg DE