FAN-OUT WAFER LEVEL CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

摘要

A fan-out wafer level chip package structure and the manufacturing method thereof are provided. The method includes the steps of providing a supporting plate having a removable tape formed on the supporting plate, placing a plurality of chips on the removable tape, applying an adhesive layer on a back surface of each of the chips, providing a conductive cover for covering all chips and isolating the chips from each other by a plurality of partitions, injecting a molding compound into an inside of the conductive cover and curing the molding compound for forming an encapsulation, separating the encapsulation from the supporting plate, forming a connection layer on an active surface of each of the chips to establish electrical connections, and performing a cutting process to divide the encapsulation into a plurality of the package structures.

主权项

1. A manufacturing method of a fan-out wafer level chip package structure comprising:
providing a supporting plate having a supporting surface and a removable tape formed on the supporting surface; disposing a plurality of chips on the removable tape, wherein each of the chips has an active surface and a back surface, and each of the chips is attached to the removable tape with the active surface; applying an adhesive layer on the back surface of each of the chips; providing a conductive cover having a bottom plate and a plurality of partition plates arranged on the bottom plate, wherein the partition plates define a plurality of accommodating regions; attaching the conductive cover to the supporting surface to cover the chips, wherein the chips are respectively arranged in the accommodating regions and isolated from each other by the partition plates; injecting a molding compound into an inside of the conductive cover to fill a space formed between the chips and the partition plates; performing a curing process to form an encapsulation; separating the encapsulation from the supporting plate, wherein the active surfaces of the chips are located at a first surface of the encapsulation; forming an connection layer on the first surface of the encapsulation to connect the chips; and performing a cutting process to divide the encapsulation into a plurality of package structures, wherein each of the package structures includes a conductive frame formed by cutting the conductive cover and a wiring layer formed by cutting the connection layer.