发明名称 |
Variable clocked serial array processor |
摘要 |
A serial array processor may have an execution unit, which is comprised of a multiplicity of single bit arithmetic logic units (ALUs), and which may perform parallel operations on a subset of all the words in memory by serially accessing and processing them, one bit at a time, while an instruction unit of the processor is pre-fetching the next instruction, a word at a time, in a manner orthogonal to the execution unit. |
申请公布号 |
US9329621(B2) |
申请公布日期 |
2016.05.03 |
申请号 |
US201314100344 |
申请日期 |
2013.12.09 |
申请人 |
Cooke Laurence H. |
发明人 |
Cooke Laurence H. |
分类号 |
G06F9/30;G06F1/06;G06F15/78;G06F15/80;G11C11/405 |
主分类号 |
G06F9/30 |
代理机构 |
Panitch Schwarze Belisario & Nadel LLP |
代理人 |
Panitch Schwarze Belisario & Nadel LLP |
主权项 |
1. A processor including:
an instruction unit; an operation unit configured to execute each of a series of operations, respective operations of the series of operations requiring respective pluralities of clock cycles to complete; and at least one memory; wherein a configuration of hardware within the operation unit is changed prior to executing each respective operation of the series of operations, and wherein clock frequencies of the respective pluralities of clock cycles are changed for respective operations of the series of operations. |
地址 |
Los Gatos CA US |