发明名称 INTEGRATED CIRCUIT ANALYSIS SYSTEMS AND METHODS
摘要 The current invention uses structural data mining methods and systems, combined with partitioning hints and heuristics, to locate high level library functional blocks in a gate level netlist of an integrated circuit (IC). In one embodiment of the invention, the library is created by synthesizing various design blocks and constraints. The method supports characterization matching between a netlist and a library, between libraries and between netlists. The data mining method described herein uses a subgraph growing method to progressively characterize the graph representation of the netlist of the IC. In one embodiment of the invention, alternative hashing is used to perform subgraph characterization. Further, the located high level functional blocks may be used to substitute the corresponding portions of the target netlist having the matched characterizations, and may be annotated accordingly in the resulting netlist.
申请公布号 CA2708116(C) 申请公布日期 2016.05.03
申请号 CA20102708116 申请日期 2010.06.18
申请人 SEMICONDUCTOR INSIGHTS INC. 发明人 ZAVADSKY, VYACHESLAV L.;KEYES, EDWARD
分类号 G01R31/28;G06F17/50 主分类号 G01R31/28
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