| 摘要 |
A latch circuit includes: first to N^th storage nodes (N is an even number equal to or greater than 4); first to N^th transistor pairs, where each of the first to N^th transistor pairs includes a PMOS transistor and an NMOS transistor serially connected through a corresponding storage node among the first to N^th storage nodes and each of the first to N^th storage nodes is connected to the gate of the NMOS transistor of the front transistor pair and to the gate of the PMOS transistor of the rear transistor pair; first to N^th NPMOS transistor which operates a corresponding storage node among the first to N^th storage nodes at a high level; and first to N^th NNMOS transistor which operates a corresponding storage node among the first to N^th storage nodes at a low level. When first data inputted into the latch circuit, the even-number nodes among the first to N^th storage nodes may operate at a high level by the even-number transistors among the first to N^th NPMOS transistors and the odd-number nodes among the first to N^th storage nodes may operate at a low level by the odd-number transistors among the first to N^th NNMOS transistors. |
