BIPOLAR LOGIC GATES ON MOS-BASED MEMORY CHIPS

摘要

A system uses both MOS-based and bipolar-based decoding circuitry in an address decoder for MOS-based memory. The system includes a MOS-based memory, which includes an array of a plurality of memory cells configured to store data, and an address decoder including MOS-based circuitry and bipolar logic circuitry. The address decoder is configured to accept a word comprising a plurality of bits and access the array of memory cells using the word.

主权项

1. A system, comprising:
a MOS-based memory, comprising:
an array of a plurality of memory cells configured to store data;an address decoder comprising:
MOS-based circuitry; andbipolar logic circuitry;wherein the address decoder is configured to:
accept a word comprising a plurality of bits; andaccess the array of memory cells using the word.