发明名称 |
SYSTEM FOR REDUCING POWER CONSUMPTION OF INTEGRATED CIRCUIT |
摘要 |
A method for reducing dynamic power consumption of an integrated circuit design having flip-flops with an EDA tool that initiates clock gating by gating a clock signal received by the flip-flops. A first set of positive-edge triggered flip-flops and a second set of negative-edge triggered flip-flops, and a first set of OR-type clock gating cells and a second set of AND-type clock gating cells are selected from a technology library. The OR-type clock gating cells are connected to clock input terminals of the first set of positive-edge triggered flip-flops and the AND-type clock gating cells to clock terminals of the second set of negative-edge triggered flip-flops. |
申请公布号 |
US2016117429(A1) |
申请公布日期 |
2016.04.28 |
申请号 |
US201414523958 |
申请日期 |
2014.10.27 |
申请人 |
Jain Rahul;Dhamija Nitin;Lohani Umesh Chandra |
发明人 |
Jain Rahul;Dhamija Nitin;Lohani Umesh Chandra |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
Noida IN |