发明名称 Interconnect Structure for Wafer Level Package
摘要 A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI.
申请公布号 US2016118272(A1) 申请公布日期 2016.04.28
申请号 US201514981204 申请日期 2015.12.28
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Yu Chen-Hua;Lin Jing-Cheng;Liu Nai-Wei;Hung Jui-Pin;Jeng Shin-Puu
分类号 H01L21/48;H01L21/56;H01L21/78 主分类号 H01L21/48
代理机构 代理人
主权项 1. A method comprising: forming a dielectric layer over a device wafer, the device wafer comprising: a device die region having a substrate;a metal pad over the substrate; anda metal pillar over and contacting the metal pad, wherein the device die region is covered by the dielectric layer, and wherein the dielectric layer contacts a sidewall of the metal pillar; and separating the device die region from additional device die regions in the device wafer to form a device die, wherein no patterning is performed to the dielectric layer between forming the dielectric layer and separating the device die region.
地址 Hsin-Chu TW