Pseudo dual port memory with dual latch flip-flop

摘要

A memory and a method for operating the memory provided. In one aspect, the memory may be a PDP memory. The memory includes a control circuit configured to generate a first clock and a second clock in response an edge of a clock for an access cycle. A first input circuit is configured to receive an input for a first memory access based on the first clock. The first input circuit includes a latch. The second input circuit configured to receive an input for a second memory access based on the second clock. The second input circuit includes a flip-flop.

主权项

1. A memory comprising:
a control circuit configured to generate a first clock and a second clock in response to an edge of a clock for an access cycle; a first input circuit configured to receive an input for a first memory access based on the first clock, wherein the first input circuit includes a latch; and a second input circuit configured to receive an input for a second memory access, the second memory access being after the first memory access, based on the second clock, wherein the second input circuit includes a flip-flop,
wherein the first input circuit latches the input for the first memory access in response to a transition of the first clock, andthe second input circuit latches the input for the second memory access in response to a transition of the second clock, while the input for the first memory access is latched.