发明名称 |
Array substrate and liquid crystal display panel comprising dual gate lines having TFT and pixel connection between the gate lines |
摘要 |
Embodiments provide an array substrate and a liquid crystal display panel. The array substrate comprises: a substrate, data lines and gate lines which are provided on the substrate and intersect with each other, and sub-pixel units which are defined by surrounding of the data lines and the gate lines and are arranged in an array form. Two gate lines for respectively driving the sub-pixel units in two adjacent rows are located between the sub-pixel units in the two adjacent rows; each sub-pixel unit comprises a thin film transistor (TFT) and a pixel electrode, and a connection area of the TFT and the pixel electrode is located between the two gate lines adjacent to the sub-pixel unit and has no overlapping area with a projection of the two gate lines in a perpendicular direction of the array substrate. |
申请公布号 |
US9323122(B2) |
申请公布日期 |
2016.04.26 |
申请号 |
US201313895502 |
申请日期 |
2013.05.16 |
申请人 |
BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. |
发明人 |
Jiang Wenbo;Xue Hailin;Dong Xue;Che Chuncheng;Chen Dong |
分类号 |
G02F1/136;G02F1/1362;H01L27/12;G02F1/1343 |
主分类号 |
G02F1/136 |
代理机构 |
Ladas & Parry LLP |
代理人 |
Ladas & Parry LLP |
主权项 |
1. An array substrate, comprising:
a substrate, data lines and gate lines which are provided on the substrate and intersect with each other, and sub-pixel units which are defined by surrounding of the data lines and the gate lines and are arranged in an array form; wherein two gate lines for respectively driving the sub-pixel units in two adjacent rows are located between the sub-pixel units in the two adjacent rows, and wherein each sub-pixel unit comprises a thin film transistor (TFT) and a pixel electrode, the TFT and the pixel electrode are electrically connected so as to function as a switch element, and a connection area of the TFT and the pixel electrode is located between the two gate lines adjacent to the sub-pixel unit and has no overlapping area with a projection of the two gate lines in a perpendicular direction of the array substrate. |
地址 |
Beijing CN |