| 主权项 |
1. A Gate Driver on Array (GOA) circuit comprising M cascaded GOA units, wherein:
the M cascaded GOA units have a one-to-one correspondence with M rows of pixels within a pixel region, a first GOA unit of the M cascaded GOA units corresponds to an n-th row of the M rows of pixels, n is a natural number less than M, a second GOA unit of the M cascaded GOA units corresponds to an (n+1)-th row of the M rows of pixels, each of the M cascaded GOA units outputs a Gate signal and a Reset signal, the second GOA unit comprises: (i) a Reset signal output module configured to receive a Reset input signal and output the Reset signal and (ii) a Gate signal output module configured to receive a Gate input signal and output the Gate signal, the Gate signal output from the first GOA unit is connected as the Reset input signal of the second GOA unit and the Gate input signal of the second GOA unit, the Reset signal output module includes (i) a first clock signal input terminal CLK1, (ii) a second clock signal input terminal CLK2, (iii) a third clock signal input terminal CLK3, (iv) a signal input terminal, (v) a Reset signal output terminal, (vi) a first thin film transistor, (vii) a second thin film transistor, (viii) a third thin film transistor, (ix) a fourth thin film transistor, (x) a fifth thin film transistor, and (xi) a sixth thin film transistor, a gate electrode of the first thin film transistor is connected to a drain electrode of the fifth thin film transistor, a source electrode of the first thin film transistor is connected to the CLK2, and a drain electrode of the first thin film transistor is connected to the Reset signal output terminal so as to output the Reset signal to outside, and a first capacitor is connected between the gate electrode and the drain electrode of the first thin film transistor, a gate electrode of the second thin film transistor is connected to a high level via a second capacitor, the gate electrode of the second thin film transistor is connected to a drain electrode of the third thin film transistor, a source electrode of the second thin film transistor is connected to the high level, and a drain electrode of the second thin film transistor is connected to the Reset signal output terminal so as to output the Reset signal to outside, a gate electrode of the third thin film transistor is connected to the CLK3, a source electrode of the third thin film transistor is connected to a low level, and a drain electrode of the third thin film transistor is connected to a drain electrode of the fourth thin film transistor, a gate electrode of the fourth thin film transistor is connected to the signal input terminal, a source electrode of the fourth thin film transistor is connected to the high level, and the drain electrode of the fourth thin film transistor is connected to the drain electrode of the third thin film transistor, a gate electrode of the fifth thin film transistor is connected to the CLK1, a source electrode of the fifth thin film transistor is connected to the signal input terminal, a drain electrode of the fifth thin film transistor is connected to the gate electrode of the first thin film transistor, and the drain electrode of the fifth thin film transistor is connected to a drain electrode of the sixth thin film transistor, and a gate electrode of the sixth thin film transistor is connected to the high level via the second capacitor, the gate electrode of the sixth thin film transistor is connected to the drain electrode of the third thin film transistor, a source electrode of the sixth thin film transistor is connected to the high level, and the drain electrode of the sixth thin film transistor is connected to the drain electrode of the fifth thin film transistor. |
