发明名称 高性能サブシステムの設計および組立体
摘要 PROBLEM TO BE SOLVED: To provide multiple integrated circuit chip structure for performing inter-chip communication between integrated circuit chips having structure including neither an ESD protection circuit nor an input/output circuit.SOLUTION: Multiple integrated circuit chip structure comprises an inter-chip interface circuit 360 configured to selectively connect an internal circuit of an integrated circuit so as to test an interface circuit 385, having an ESD protection circuit 387 and an input/output circuit 389, for communicating with an external test system during a test and a burn-in procedure. Multiple wiring integrated circuit chip structure comprises a first integrated circuit chip 305 attached to one or more second integrated circuit chips 310 for physically and electrically connecting integrated circuit chips mutually.
申请公布号 JP5908545(B2) 申请公布日期 2016.04.26
申请号 JP20140165234 申请日期 2014.08.14
申请人 クゥアルコム・インコーポレイテッドQUALCOMM INCORPORATED 发明人 ムウ−シュン・リン
分类号 H01L25/065;H01L21/822;H01L25/07;H01L25/18;H01L27/04 主分类号 H01L25/065
代理机构 代理人
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