发明名称 Shielded coplanar line
摘要 In one embodiment there is disclosed a method for manufacturing an integrated circuit in a semiconductor substrate including through vias and a coplanar line, including the steps of: forming active components and a set of front metallization levels; simultaneously etching from the rear surface of the substrate a through via hole and a trench crossing the substrate through at least 50% of its height; coating with a conductive material the walls and the bottom of the hole and of the trench; and filling the hole and the trench with an insulating filling material; and forming a coplanar line extending on the rear surface of the substrate, in front of the trench and parallel thereto, so that the lateral conductors of the coplanar line are electrically connected to the conductive material coating the walls of the trench.
申请公布号 US9324612(B2) 申请公布日期 2016.04.26
申请号 US201313899326 申请日期 2013.05.21
申请人 STMicroelectronics SA 发明人 Joblot Sylvain;Bar Pierre
分类号 H01L23/48;H01L23/52;H01L21/768;H01P3/00;H01P11/00 主分类号 H01L23/48
代理机构 Seed IP Law Group PLLC 代理人 Seed IP Law Group PLLC
主权项 1. An integrated circuit comprising: a semiconductor substrate having a first surface spaced apart from a second surface by a thickness, a hole in the second surface of the substrate, the hole extending through at least 50% of the thickness of the substrate and forming walls and a bottom within the substrate; a conductive material covering the walls; an insulating material located in the hole over the conductive material; and a coplanar line that is configured to convey radio frequency signals located over the second surface of the substrate, the coplanar line including first and second lateral conductors that are located on opposing sides of a central conductor, the central conductor facing the hole, and wherein the lateral conductors of the coplanar line are electrically coupled to said conductive material that is covering the walls.
地址 Montrouge FR