METHOD AND APPARATUS FOR TESTING MEMORY

摘要

In an integrated circuit, a first scan chain of flip-flops is loaded with data for testing data retention of the flip-flops and a memory is loaded with data for performing a retention test by a memory built-in self-test (MBIST) wrapper circuit. A portion of the system is placed in a low-power state for a predetermined period of time before data is read from the memory and retention of data by the memory while in the low-power state is determined.

主权项

1. A method of testing operation of a memory of an integrated circuit, comprising:
loading a first scan chain of flip-flops with first data for testing data retention of the flip-flops; loading the memory with second data for performing a retention test by a memory built-in self-test (MBIST) wrapper circuit; placing at least a portion of the integrated circuit and the memory in a low-power state for a predetermined period of time; reading the second data from the memory; and determining retention of the second data by the memory in the low-power state based on the read data.