发明名称 APPARATUSES AND METHODS FOR SEGMENTED SGS LINES
摘要 Apparatuses and methods for segmented SGS lines are described. An example apparatus ma include first and second pluralities of memory subblocks of a memory block. The apparatus may include a first select gate control line associated with the first plurality of memory subblocks and a second select gate control line associated with the second plurality of memory subblocks. The first select gate control line may be coupled to a first plurality of select gate switches of the first plurality of memory subblocks. The second select gate control line may be coupled to a second plurality of select gate switches of the second plurality of memory subblocks. The first and second pluralities of select gate switches may be coupled to a source. The apparatus may include a plurality of memory access lines associated with each the first and second pluralities of memos subblocks.
申请公布号 US2016111160(A1) 申请公布日期 2016.04.21
申请号 US201414518807 申请日期 2014.10.20
申请人 MICRON TECHNOLOGY, INC. 发明人 PAN FENG;PARK JAEKWAN;GHODSI RAMIN
分类号 G11C16/04;G11C16/26 主分类号 G11C16/04
代理机构 代理人
主权项 1. An apparatus, comprising: a first plurality of memory subblocks of a memory block; a second plurality of memory subblocks of the memory block; a first select gate control line associated with the first plurality of memory subblocks, the first select gate control line coupled to a first plurality of select gate switches of the first plurality of memory subblocks, the first plurality of select gate switches coupled to a source; a second select gate control line associated with the second plurality of memory subblocks, the second select gate control line coupled to a second plurality of select gate switches of the second plurality of memory subblocks, the second plurality of select gate switches coupled to the source; and a plurality of memory access lines, each memory access line of the plurality of memory access lines associated with each memory subblock of the first plurality of memory subblocks and each memory subblock of the second plurality of memory subblocks.
地址 Boise ID US