发明名称 FinFET device and method of fabricating same
摘要 The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having isolation regions, a gate region, source and drain regions separated by the gate region, a first fin structure in a gate region. The first fin structure includes a first semiconductor material layer as a lower portion of the first fin structure, a semiconductor oxide layer as an outer portion of a middle portion of the first fin structure, the first semiconductor material layer as a center portion of the middle portion of the first fin structure and a second semiconductor material layer as an upper portion of the first fin structure. The semiconductor device also includes a source/drain feature over the substrate in the source/drain region between two adjacent isolation regions and a high-k (HK)/metal gate (MG) stack in the gate region, wrapping over a portion of the first fin structure.
申请公布号 US9318606(B2) 申请公布日期 2016.04.19
申请号 US201313902322 申请日期 2013.05.24
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Wang Chih-Hao;Ching Kuo-Cheng;Chang Gwan Sin;Wu Zhiqiang
分类号 H01L21/336;H01L29/78;H01L21/02;H01L29/66;H01L29/786 主分类号 H01L21/336
代理机构 Haynes and Boone, LLP 代理人 Haynes and Boone, LLP
主权项 1. A semiconductor device comprising: a substrate having a gate region and source and drain (S/D) regions; a first fin structure in the gate region, the first fin structure including: a first semiconductor material that is a portion of the substrate;a second semiconductor material disposed on the first semiconductor material;a third semiconductor material disposed on the second semiconductor material; anda semiconductor oxide disposed on an outer side surface of the second semiconductor material; and a high-k (HK)/metal gate (MG) stack in the gate region, the HK/MG stack wrapping over a portion of the first fin structure, wherein the HK/MG stack includes: an interfacial layer disposed on the semiconductor oxide and the third semiconductor material; anda high-K dielectric layer over and contacting the interfacial layer, wherein the high-K dielectric layer physically contacts two opposing side surfaces of the interfacial layer and a top surface of the interfacial layer there between; and S/D features in the S/D region.
地址 Hsin-Chu TW
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