Concurrent multiple instruction issue of non-pipelined instructions using non-pipelined operation resources in another processing core

摘要

A method and circuit arrangement utilize inactive non-pipelined operation resources in one processing core of a multi-core processing unit to execute non-pipelined instructions on behalf of another processing core in the same processing unit. Adjacent processing cores in a processing unit may be coupled together such that, for example, when one processing core's non-pipelined execution sequencer is busy, that processing core may issue into another processing core's non-pipelined execution sequencer if that other processing core's non-pipelined execution sequencer is idle, thereby providing intermittent concurrent execution of multiple non-pipelined instructions within each individual processing core.

主权项

1. A circuit arrangement, comprising:
a first processing core disposed on an integrated circuit device and including a first execution unit that includes a first non-pipelined execution logic circuit, the first non-pipelined execution logic circuit configured to execute at least one non-pipelined instruction; a second processing core disposed on the integrated circuit device and including a second execution unit that includes a second non-pipelined execution logic circuit, the second non-pipelined execution logic circuit configured to execute the at least one non-pipelined instruction; and a multiplexing logic circuit coupling together the first and second execution units to receive a plurality of non-pipelined instructions issued to each of the first and second execution units and route the plurality of non-pipelined instructions to the first non-pipelined execution logic circuit for execution thereby, wherein the second processing core is configured to selectively issue a first non-pipelined instruction to the first non-pipelined execution logic circuit using the multiplexing logic circuit and to selectively issue a second non-pipelined instruction to the second non-pipelined execution logic circuit.