LOW POWER EXTERNALLY BIASED POWER-ON-RESET CIRCUIT

摘要

Various methods and devices that involve power-on-reset (POR) circuits are disclosed herein. An exemplary POR circuit for generating a POR signal upon detecting that a supply voltage has reached a desired level comprises a sense circuit and a delayed buffer. The sense circuit comprises: (i) an inverter powered by a known bias voltage; (ii) a feedback circuit powered by the supply voltage; and (iii) an output node of the sense circuit that experiences a voltage transition when the supply voltage has reached the desired level. The delayed buffer is coupled to the output node of the sense circuit that generates the POR signal in response to the voltage transition. The feedback circuit shuts off the sense circuit in response to the voltage transition. The POR circuit generates the POR signal for a local system. The known bias voltage is provided by an external system.

主权项

1. A power-on-reset circuit for generating a power-on-reset signal upon detecting that a supply voltage has reached a desired level comprising:
a sense circuit comprising: (i) an inverter powered by a known bias voltage; (ii) a feedback circuit powered by the supply voltage; and (iii) an output node of the sense circuit that experiences a voltage transition when the supply voltage has reached the desired level; and a delayed buffer coupled to the output node of the sense circuit that generates the power-on-reset signal in response to the voltage transition; wherein the feedback circuit shuts off the sense circuit in response to the voltage transition; wherein the power-on-reset circuit generates the power-on-reset signal for a local system; and wherein the known bias voltage is provided by an external system; the sense circuit further comprising: a voltage divider coupled to the supply voltage and providing a divided voltage to an inverter input node; wherein the inverter comprises an inverter output node and the inverter input node; and wherein the inverter output node is the output node of the sense circuit; the voltage divider comprising: a first transistor that is gate coupled to the inverter input node, and that provides a first source-drain path between the supply voltage and the inverter input node; and a second transistor that is gate coupled to the inverter input node, and that provides a second source-drain path along a circuit branch between the input of the inverter and a ground node.