发明名称 Method and arrangement for verifying functional safety
摘要 A method and an arrangement for verifying the functional safety of a signal path in a power electronics device between a control unit and a gate amplifier, which control unit generates control signals for controllable power components, and which gate amplifier generates control pulses, in response to the control signals generated by the control unit, for turning the controllable power components on and off. The control signal, generated by the control unit is transmitted through a safety unit to the gate amplifier. Safety unit generates a first test signal (TEST), which is combined to the control signal (PWM41) received from the control unit such that the logic state of this first combined control signal (PWM42) corresponds to a state wherein the controllable power component is turned on during normal operation. During the active state of the first test signal the safety unit generates a second test signal (STOP), which is combined to the first combined control signal such that the logic state of this second combined test signal (PWM43) corresponds to a state wherein the controllable power component is turned off during normal operation. During the active state of the second test signal (STOP) the safety unit measures the input signal of the gate amplifier to verify that it is in a logic state wherein the controllable power component is turned off during normal operation. The duration of the test signals are such they have no effect on the final control pulse (V G4 ) of the power component generated by gate amplifier.
申请公布号 EP3007293(A1) 申请公布日期 2016.04.13
申请号 EP20140188103 申请日期 2014.10.08
申请人 VACON OY 发明人 AHO, EERO;ALASAARI, PEKKA;SIHVONEN, JUSTUS;HUTTUNEN, TEEMU
分类号 H02H7/08;G01R31/02;H02H5/10;H02H7/12;H02M1/32;H02P29/02;H03K17/00 主分类号 H02H7/08
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