发明名称 |
Semiconductor memory apparatus and data processing system with main memory blocks and redundant memory blocks sharing a common global data line |
摘要 |
A semiconductor memory apparatus includes: a memory area including a plurality of memory banks having main memory areas configured to transmit and receive data to and from the outside through a plurality of global data lines, respectively, and one or more redundancy memory areas configured to use any one of the global data lines as a common global data line; and a controller configured to control data to be transmitted and received through the common global data line, as a redundancy program mode, a redundancy read mode, or a redundancy erase mode is enabled. |
申请公布号 |
US9312032(B2) |
申请公布日期 |
2016.04.12 |
申请号 |
US201514943252 |
申请日期 |
2015.11.17 |
申请人 |
SK hynix Inc. |
发明人 |
Kim Min Su |
分类号 |
G11C29/00;G11C7/10 |
主分类号 |
G11C29/00 |
代理机构 |
William Park & Associates Ltd. |
代理人 |
William Park & Associates Ltd. |
主权项 |
1. A semiconductor memory apparatus comprising:
a main memory area comprising a plurality of banks; one or more redundancy memory areas; a plurality of global data lines configured to exchange data of respective banks with the outside; a main page buffer coupled to the main memory area; redundancy page buffers coupled to respective redundancy memory areas; and a controller configured to control a redundancy program mode in which, as a program command, an access address, and data are provided, the data is inputted to the main page buffer, and the data of the main page buffer is transferred to a corresponding redundancy page buffer when the main memory area is repaired, wherein one or more of the global data lines comprise a common global data line which is commonly shared by the redundancy memory areas and the main memory area; and wherein the controller sets the main page buffer in a program-inhibited state, after the data of the main page buffer is transferred to the corresponding redundancy page buffer. |
地址 |
Icheon-si Gyeonggi-do KR |