| 摘要 |
PURPOSE:To ensure the start-up of an interface circuit by preventing an oscillating frequency of the phase locked loop from being fixed at a frequency different from the frequency of a transmission signal. CONSTITUTION:A PLL control circuit 15 measures a period when a lock detection section 14 detects the synchronization between a transmission signal DIN and a reference clock BCK and when a specific period elapses in the process of measurement, a phase comparator 11 of the phase locked loop 10 and a voltage controlled oscillator 13 are reset. Since the reset phase locked loop 10 controls the oscillation of the voltage controlled oscillator 13 so that the reference clock BCK is synchronized with the transmission signal DIN, the starting of the phase locked loop 10 is ensured. |
