TECHNIQUES FOR DATA RETENTION IN MEMORY CELLS DURING POWER INTERRUPTION

摘要

Volatile memory is described, comprising: (i) a first inverter comprising a first p-type field effect transistor (FET) connected to a first n-type FET; (ii) a second inverter comprising a second p-type FET connected to a second n-type FET; (iii) a third p-type FET; (iv) a fourth p-type FET; and (v) a floating line connecting (i) a source of the third p-type FET, and (ii) a source of the fourth p-type FET, wherein: (a) the first data line is connected to: a gate of the second p-type FET, a gate of the second n-type FET, a drain of the third p-type FET, and a gate of the fourth p-type FET, and (b) the second data line is connected to: a gate of the first p-type FET, a gate of the first n-type FET, a drain of the fourth p-type FET, and a gate of the third p-type FET.

主权项

1. Apparatus comprising a volatile memory, the volatile memory having a first data line and a second data line, and comprising:
a first inverter comprising a first p-type field effect transistor (FET) connected to a first n-type FET; a second inverter comprising a second p-type FET connected to a second n-type FET, and cross-coupled with the first inverter; a third p-type FET; a fourth p-type FET; and a floating line connecting (i) a source of the third p-type FET, and (ii) a source of the fourth p-type FET,wherein:
the first data line is connected to:
a gate of the second p-type FET,a gate of the second n-type FET,a drain of the third p-type FET, anda gate of the fourth p-type FET, and the second data line is connected to:
a gate of the first p-type FET,a gate of the first n-type FET,a drain of the fourth p-type FET, anda gate of the third p-type FET.