| 摘要 |
A digital-to-analog converter (DAC) including a DAC core circuit having a plurality of input lines each being responsive to a digital bit input signal and an output line outputting a converted analog signal of the digital bits. The DAC also includes a clock circuit responsive to a clock input signal at one frequency and outputting a clock output signal at another frequency. The DAC also includes a clock tree distribution network responsive to the clock output signal from the clock circuit and splitting the clock output signal into a plurality of split clock signals that are applied to the DAC core circuit, where the DAC core circuit is fabricated in an indium phosphide (InP) semiconductor material and the clock tree distribution network is fabricated in a silicon germanium (SiGe) semiconductor material. |
