发明名称 |
CLOCK-FREE DUAL-DATA-RATE LINK WITH BUILT-IN FLOW CONTROL |
摘要 |
A dual-data-rate interface is provided that includes a transmitter driving a transmit pin coupled to a receive pin of a receiver. The receiver drives its receive pin with cycles of a fetch clock. The transmitter responds to each edge of the fetch clock by transmitting a bit over the transmit pin to the receiver. |
申请公布号 |
WO2016053796(A1) |
申请公布日期 |
2016.04.07 |
申请号 |
WO2015US52351 |
申请日期 |
2015.09.25 |
申请人 |
QUALCOMM INCORPORATED |
发明人 |
MISHRA, LALAN, JEE;WIETFELDT, RICHARD;PANIAN, JAMES |
分类号 |
G06F13/42 |
主分类号 |
G06F13/42 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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