发明名称 SYSTEM AND METHOD FOR PRE-ENCODING OF DATA FOR DIRECT WRITE TO MULTI-LEVEL CELL MEMORY
摘要 A method and system for reducing data transfers between memory controller and multi-level cell (MLC) non-volatile memory during programming passes of a word line (WL) in the non-volatile memory. The system includes a controller and non-volatile memory having multiple WLs, each WL having a plurality of MLC memory cells. The controller stores received data in volatile memory until a target WL amount of data is received. The controller pre-encodes the received data into direct WL programming data for each programming pass necessary to program a target MLC WL. All direct WL programming data for all programming passes are stored in the volatile memory before programming. Different portions of direct WL programming data are transmitted from the controller to the non-volatile memory each pass. The received data may be deleted from the volatile memory before transmitting at least a portion of the direct WL programming data to the non-volatile memory.
申请公布号 US2016098319(A1) 申请公布日期 2016.04.07
申请号 US201414505291 申请日期 2014.10.02
申请人 SanDisk Technologies Inc. 发明人 Gorobets Sergey Anatolievich
分类号 G06F11/10;G11C16/10;G11C29/52;G11C11/56 主分类号 G06F11/10
代理机构 代理人
主权项 1. A non-volatile memory system comprising: a multi-level cell (MLC) non-volatile memory having a plurality word lines, each word line (WL) having a plurality of MLC memory cells and programmable in a plurality of programming passes; and circuitry comprising: volatile memory configured to receive, in a first portion, an amount of data from a data source, the amount of received data corresponding to a storage capacity of a word line (WL) in the MLC non-volatile memory;a pre-encoding engine configured to convert the amount of received data in the first portion into direct WL programming data for all of the plurality of programming passes to be performed in one of the plurality of word lines, and to store the direct WL programming data for all of the plurality of programming passes for the one of the plurality of wordlines in a second portion of the volatile memory; anda processor configured to transmit a different portion of the direct WL programming data from the second portion to the one of the plurality of wordlines for each of the plurality of programming passes.
地址 Plano TX US