| 主权项 |
1. A processor comprising:
a plurality of cores, at least one of the plurality of cores including a decoder to decode instructions, at least one execution unit to execute the decoded instructions, and at least one core-included cache memory, wherein the at least one of the plurality of cores comprises an out-of-order pipeline; a shared cache memory; an integrated memory controller; and a power control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores, wherein the first core and the second core are to execute asymmetric workloads, the power control logic to determine whether to update the voltage/frequency of the first core based at least in part on a workload and a temperature of the processor, and responsive to the determination to update the voltage/frequency provided to the first core, wherein the power control logic is to send a control signal to a voltage regulator to cause the voltage regulator to provide the updated voltage to the first core. |
