发明名称 Data coherency management
摘要 A data processing systems employing a coherent memory system comprises multiple main cache memories. An inclusive snoop directory memory stores directory lines. Each directory line includes a directory tag and multiple snoop vectors. Each snoop vector relates to a span of memory addresses corresponding to the cache line size within the main cache memories.
申请公布号 US9304923(B2) 申请公布日期 2016.04.05
申请号 US201313795680 申请日期 2013.03.12
申请人 ARM Limited 发明人 Tune Andrew David
分类号 G06F12/00;G06F12/08 主分类号 G06F12/00
代理机构 Nixon & Vanderhye P.C. 代理人 Nixon & Vanderhye P.C.
主权项 1. Apparatus for processing data comprising: a plurality of main cache memories each having a plurality of main cache lines; an inclusive snoop directory memory having a plurality of directory lines, each of said directory lines respectively storing: (i) a given directory tag value indicative of a contiguous range of memory address values with a given span corresponding in size to N main cache lines, where N is an integer greater than one; and(ii) N snoop vectors, each of said N snoop vectors indicating at least that, for a respective one of N memory address sub-regions within said given span, one or more of said plurality of main cache memories is logged as storing data corresponding to said respective one of N memory address sub-regions, wherein: said inclusive snoop directory memory comprises A directory lines, where A is a positive integer; said plurality of main cache memories comprise X cache memories, where X is an integer greater than one; each of said plurality of main cache memories comprises B main cache lines, where B is a positive integer; and N*A is greater than X*B.
地址 Cambridge GB