主权项 |
1. A method for forming a chip package comprising:
forming a first lower vertical connection, a plurality of second lower vertical connections and a third lower vertical connection in a substrate of at least one semiconductor device; forming a chip select terminal and a plurality of chip select pads on the substrate, wherein the chip select terminal connects to the first lower vertical connection, and wherein the plurality of chip select pads correspondingly connect to the plurality of second lower vertical connections; forming an insulation layer on the substrate; forming a plurality of upper vertical connections in the insulation layer, wherein the plurality of upper vertical connections correspondingly connect to the plurality of chip select pads and the third lower vertical connection, and in which the third lower vertical connection and a corresponding one of the upper vertical connections form a vertical through connection that goes straight through the substrate and the insulation layer; forming a plurality of conductors on the insulation layer, wherein the plurality of conductors correspondingly connect to the plurality of upper vertical connections and the vertical through connection; and forming an insulation pad on one of the plurality of conductors, wherein the one of the plurality of conductors on which the insulation pad is formed connects with the vertical through connection, wherein the first lower vertical connection, the plurality of second lower vertical connections and the third lower vertical connection are arranged in two dimensions, and wherein a maximum width of the insulation pad is substantially the same as a maximum width of the vertical through connection. |