Semiconductor integrated circuit device and manufacturing method thereof

摘要

In order to achieve high-speed operation of an eDRAM, the eDRAM includes: a selection MISFET having a gate electrode that serves as a word line, a source region, and a drain region; a source plug electrode coupled to the source region; and a drain plug electrode coupled to the drain region DR1. The eDRAM further includes: a capacitive plug electrode coupled to the drain plug electrode; a bit line coupled to the source plug electrode; a stopper film covering the bit line; and a capacitive element that is formed over the stopper film and has a first electrode, a dielectric film, and a second electrode. The first electrode is coupled to the capacitive plug electrode, and the height of the capacitive plug electrode and that of the bit line are equal to each other.

主权项

1. A semiconductor integrated circuit device comprising:
a semiconductor substrate; a word line extending in a first direction in a main surface of the semiconductor substrate; a bit line extending in a second direction that intersects with the first direction in the main surface of the semiconductor substrate; a gate electrode that is formed in the main surface of the semiconductor substrate and serves as the word line; a MISFET having a source region and a drain region that are formed in the main surface of the semiconductor substrate so as to sandwich the gate electrode; a first interlayer insulating film that is formed over the main surface of the semiconductor substrate so as to cover the MISFET; a source plug electrode that penetrates the first interlayer insulating film to be electrically coupled to the source region; a drain plug electrode that penetrates the first interlayer insulating film to be electrically coupled to the drain region; a second interlayer insulating film formed over the first interlayer insulating film; a capacitive plug electrode that penetrates the second interlayer insulating film to be electrically coupled to the drain plug electrode; the bit line that penetrates the second interlayer insulating film to be electrically coupled to the source plug electrode; a first insulating film covering the bit line; and a capacitive element that is formed over the first insulating film and has a first electrode, a dielectric film, and a second electrode, wherein the first electrode is electrically coupled to the capacitive plug electrode, and wherein a height of the capacitive plug electrode and that of the bit line are equal to each other.