发明名称 |
System and method for lithography alignment |
摘要 |
The present disclosure provides one embodiment of a lithography system for integrated circuit making. The system includes a substrate stage designed to secure a substrate and being operable to move the substrate; an alignment module that includes a tunable light source being operable to generate an infrared light with a wavelength tunable; and a detector to receive the light; and an exposing module integrated with the alignment module and designed to performing an exposing process to a resist layer coated on the substrate. |
申请公布号 |
US9304403(B2) |
申请公布日期 |
2016.04.05 |
申请号 |
US201313732913 |
申请日期 |
2013.01.02 |
申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
Lin Yu-Hsien;Hsieh Hung-Chang;Shiu Feng-Jia;Lee Chun-Yi |
分类号 |
G03B27/42;G03B27/54;G03B27/32;G03F7/20;G03F9/00;G03B27/58 |
主分类号 |
G03B27/42 |
代理机构 |
Haynes and Boone, LLP |
代理人 |
Haynes and Boone, LLP |
主权项 |
1. A method, comprising:
providing an integrated circuit (IC) substrate having a first alignment mark, a second alignment mark, and a first circuit pattern defined in a first pattern layer and a third alignment mark, a fourth alignment mark, and a second circuit pattern defined in a second pattern layer; illuminating the first and second alignment marks, through a photomask, with a first light to determine a first layer alignment error including a first alignment error in relation to the first alignment mark and a second alignment error in relation to the second alignment mark, wherein the first alignment error has more weight than the second alignment error; illuminating the third and fourth alignment marks, through the photomask, with a second light to determine a second layer alignment error including a third alignment error in relation to the third alignment mark and a fourth alignment error in relation to fourth alignment mark, wherein the third alignment error has more weight than the fourth alignment error; determining a collective alignment error including the first layer alignment error in relation to the first circuit pattern and the second layer alignment error in relation to the second circuit pattern; and adjusting alignment between the IC substrate and the photomask to minimize the collective alignment error. |
地址 |
Hsin-Chu TW |