| 主权项 |
1. An apparatus of three-dimensional integrated-circuit (3D-IC) chip using a fault-tolerant test through-silicon-via (TSV), comprising
a 3D-IC chip, said 3D-IC chip comprising a first sub-chip and a second sub-chip, said second sub-chip being located on said first sub-chip; a TSV part, said TSV part being located between said first sub-chip and said second sub-chip, said TSV part comprising a plurality of TSVs and a test TSV, each of said TSVs having a first multiplexer at an input terminal and a second multiplexer at an output terminal, said test TSV having a third multiplexer at an input terminal and a demultiplexer at an output terminal,
wherein said TSV part transfers signals between said first sub-chip and said second sub-chip; and said test TSV is used as a redundant TSV to repair signal of one of said TSVs when said one of said TSVs fails; two normal logic function circuits, said normal logic function circuits being located in said first and second sub-chips, said normal logic function circuits being connected with said TSVs, said first multiplexers and said second multiplexers,
wherein said normal logic function circuits transmit signals through said TSVs; and two 3D-IC test logic circuits, said 3D-IC test logic circuits being located in said first and second sub-chips, said 3D-IC test logic circuits being connected with said test TSV, said third multiplexer and said demultiplexer,
wherein said 3D-IC test logic circuits transfer test data between said first sub-chip and said second sub-chip through said test TSV and output test result. |
