Distributed data return buffer for coherence system with speculative address support

摘要

The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. Each processor has an associated return buffer allowing out of order responses of memory read data and cache snoop responses to ensure maximum bandwidth at the endpoints, and all endpoints receive status messages to simplify the return queue.

主权项

1. A Multicore Shared Memory Controller comprising of:
a plurality of return buffers, each return buffer associated with a corresponding one of a plurality of CPUs; each return buffer including a pre data message buffer, each return buffer initiating a pre data message for each memory request and snoop request by said corresponding CPU, each pre data message including the following status information
an identification number of the originating memory request,a ready bit operable as a time stamp for the status match of the corresponding entry and indicating the start of the waiting period for the snoop response,a force-linear bit indicating an order of dataphase returns of each CPU's cache miss request,a shareable bit indicating whether the snoop request response should be counted by the return buffer,a memory read valid bit indicating that the corresponding memory access response has been received by the return buffer,a snoop response valid bit indicating that the corresponding snoop access response has been received by the return buffer,a memory access error bit indicating a memory access error, anda snoop response error bit indicating a snoop response error.