发明名称 MULTIPLICATION CIRCUIT AND MULTIPLICATION METHOD THEREOF
摘要 PROBLEM TO BE SOLVED: To perform multiplication in a parallel mode using a simple circuit.SOLUTION: A multiplication circuit has: a partial product generation circuit having a booth decoder 11 for decoding a combination of multipliers and a booth selector 12 for generating the partial product of a multiplicand and the multiplier in accordance with the result of decoding; a partial product addition circuit in which carry preservation adders for adding a plurality of partial products in parallel are arranged in tree form, and the addition data and carry data outputted by the carry preservation adder at a prescribed stage are added by the carry preservation adder at the subsequent stage; and a correction hot bit generation unit for generating, in a parallel mode for multiplying a plurality of data in parallel, a correction hot bit to be added for correction in accordance with the result of decoding of high-order side parallel data.SELECTED DRAWING: Figure 6
申请公布号 JP2016045685(A) 申请公布日期 2016.04.04
申请号 JP20140169142 申请日期 2014.08.22
申请人 FUJITSU LTD 发明人 KITAMURA KENICHI
分类号 G06F7/533 主分类号 G06F7/533
代理机构 代理人
主权项
地址